Generally, nonvolatile memory devices are configured to store and erase data electrically and retain the stored data even if a power supply to the memory device is interrupted. Nonvolatile memory devices typically have a stacked gate electrodes including a gate insulating layer, a floating gate, a dielectric layer and a control gate sequentially stacked gate structure on an active region of a substrate. In order to easily program and/or erase data from the memory device a coupling ratio should typically be high. The coupling ratio may be represented as a ratio between a voltage applied to the control gate and a voltage induced to the floating gate. Typically, the coupling ratio may be increased by having the dielectric layer and the control gate be adjacent to a side surface as well as a upper surface of the floating gate.
Referring to FIGS. 1A to 1C, cross-sections of memory devices illustrating conventional methods of increasing the coupling ratio will be discussed. As illustrated in FIG. 1A, an active region is defined on a substrate 10 by an isolation layer 16. A gate insulating layer 12 and a floating gate pattern 14 are formed on the active region. The side surface of the floating gate pattern 14 is exposed by etching the isolation layer 16 in order to possibly increase the coupling ratio. At this time, the etching of the isolation layer 16 may be performed using, for example, a dry etching process, a wet etching process, or the like. When a wet etching process having isotropic etching characteristic is used, the gate insulating layer 12 may be also etched during the wet etching process used to expose the side surface of the floating gate pattern 14.
Therefore, the isolation layer 16 is etched using a two step process. Referring first to FIG. 1B, a first etching process may be performed using, for example, a dry or wet etching process, on the isolation layer 16auntil at least a portion of the gate insulating layer 12 is exposed. As illustrated in FIG. 1C, a second etching process is performed using a dry etching process having anisotropic etching characteristic in order to etch the isolation layer 16baround the gate insulating layer 12. In this case, however, charges generated due to plasma, which may be used as an etchant during the dry etching process, may be accumulated in the floating gate pattern 14. Furthermore, because of a strong electric field due to the accumulated charges, a breakdown may be induced in the thin gate insulating layer 12. This breakdown in the gate insulating layer 12 may be detrimental to the characteristics of a transistor, which may cause instability in the operation of the nonvolatile memory device.